/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version: HSI 2017.1
 * Today is: Mon Aug 28 11:23:33 2017
*/


/ {
	amba_pl: amba_pl {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges ;
		axi_dma_la: dma@80420000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
			clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
			compatible = "xlnx,axi-dma-1.00.a";
			interrupt-parent = <&intc>;
			interrupts = <0 32 4>;
			reg = <0x80420000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg ;
			dma-channel@80420030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 32 4>;
				xlnx,datawidth = <0x10>;
				xlnx,device-id = <0x0>;
			};
		};
		axi_dma_osc0: dma@80400000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
			clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
			compatible = "xlnx,axi-dma-1.00.a";
			interrupt-parent = <&intc>;
			interrupts = <0 30 4>;
			reg = <0x80400000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg ;
			dma-channel@80400030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 30 4>;
				xlnx,datawidth = <0x10>;
				xlnx,device-id = <0x1>;
			};
		};
		axi_dma_osc1: dma@80410000 {
			#dma-cells = <1>;
			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
			clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
			compatible = "xlnx,axi-dma-1.00.a";
			interrupt-parent = <&intc>;
			interrupts = <0 31 4>;
			reg = <0x80410000 0x10000>;
			xlnx,addrwidth = <0x20>;
			xlnx,include-sg ;
			dma-channel@80410030 {
				compatible = "xlnx,axi-dma-s2mm-channel";
				dma-channels = <0x1>;
				interrupts = <0 31 4>;
				xlnx,datawidth = <0x10>;
				xlnx,device-id = <0x2>;
			};
		};
		axi_intc_0: interrupt-controller@81800000 {
			#interrupt-cells = <2>;
			compatible = "xlnx,xps-intc-1.00.a";
			interrupt-controller ;
			interrupt-parent = <&intc>;
			interrupts = <0 33 4>;
			reg = <0x81800000 0x10000>;
			xlnx,kind-of-intr = <0x3f>;
			xlnx,num-intr-inputs = <0x6>;
		};
		xadc: xadc_wiz@83c00000 {
			compatible = "xlnx,xadc-wiz-3.3";
			interrupt-parent = <&intc>;
			interrupts = <0 29 4>;
			reg = <0x83c00000 0x10000>;
			xlnx,alarm-limit-r0 = <0xb5ed>;
			xlnx,alarm-limit-r1 = <0x57e4>;
			xlnx,alarm-limit-r10 = <0x5555>;
			xlnx,alarm-limit-r11 = <0x5111>;
			xlnx,alarm-limit-r12 = <0x9999>;
			xlnx,alarm-limit-r13 = <0x91eb>;
			xlnx,alarm-limit-r14 = <0x6aaa>;
			xlnx,alarm-limit-r15 = <0x6666>;
			xlnx,alarm-limit-r2 = <0xa147>;
			xlnx,alarm-limit-r3 = <0xca33>;
			xlnx,alarm-limit-r4 = <0xa93a>;
			xlnx,alarm-limit-r5 = <0x52c6>;
			xlnx,alarm-limit-r6 = <0x9555>;
			xlnx,alarm-limit-r7 = <0xae4e>;
			xlnx,alarm-limit-r8 = <0x5999>;
			xlnx,alarm-limit-r9 = <0x5111>;
			xlnx,configuration-r0 = <0x0>;
			xlnx,configuration-r1 = <0x8100>;
			xlnx,configuration-r2 = <0x400>;
			xlnx,dclk-frequency = <0x64>;
			xlnx,external-mux-channel = "VP_VN";
			xlnx,external-muxaddr-enable = <0x0>;
			xlnx,fifo-depth = <0x7>;
			xlnx,has-axi = <0x1>;
			xlnx,has-axi4stream = <0x0>;
			xlnx,has-busy = <0x1>;
			xlnx,has-channel = <0x1>;
			xlnx,has-convst = <0x0>;
			xlnx,has-convstclk = <0x0>;
			xlnx,has-dclk = <0x1>;
			xlnx,has-drp = <0x0>;
			xlnx,has-eoc = <0x1>;
			xlnx,has-eos = <0x1>;
			xlnx,has-external-mux = <0x0>;
			xlnx,has-jtagbusy = <0x0>;
			xlnx,has-jtaglocked = <0x0>;
			xlnx,has-jtagmodified = <0x0>;
			xlnx,has-ot-alarm = <0x1>;
			xlnx,has-reset = <0x0>;
			xlnx,has-temp-bus = <0x0>;
			xlnx,has-user-temp-alarm = <0x1>;
			xlnx,has-vbram-alarm = <0x0>;
			xlnx,has-vccaux-alarm = <0x1>;
			xlnx,has-vccddro-alarm = <0x1>;
			xlnx,has-vccint-alarm = <0x1>;
			xlnx,has-vccpaux-alarm = <0x1>;
			xlnx,has-vccpint-alarm = <0x1>;
			xlnx,has-vn = <0x1>;
			xlnx,has-vp = <0x1>;
			xlnx,include-intr = <0x1>;
			xlnx,sampling-rate = "961538.4615384615";
			xlnx,sequence-r0 = <0x800>;
			xlnx,sequence-r1 = <0x303>;
			xlnx,sequence-r2 = <0x0>;
			xlnx,sequence-r3 = <0x0>;
			xlnx,sequence-r4 = <0x0>;
			xlnx,sequence-r5 = <0x0>;
			xlnx,sequence-r6 = <0x0>;
			xlnx,sequence-r7 = <0x0>;
			xlnx,sim-file-name = "design";
			xlnx,sim-file-rel-path = "./";
			xlnx,sim-file-sel = "Default";
			xlnx,vaux0 = <0x1>;
			xlnx,vaux1 = <0x1>;
			xlnx,vaux10 = <0x0>;
			xlnx,vaux11 = <0x0>;
			xlnx,vaux12 = <0x0>;
			xlnx,vaux13 = <0x0>;
			xlnx,vaux14 = <0x0>;
			xlnx,vaux15 = <0x0>;
			xlnx,vaux2 = <0x0>;
			xlnx,vaux3 = <0x0>;
			xlnx,vaux4 = <0x0>;
			xlnx,vaux5 = <0x0>;
			xlnx,vaux6 = <0x0>;
			xlnx,vaux7 = <0x0>;
			xlnx,vaux8 = <0x1>;
			xlnx,vaux9 = <0x1>;
		};
	};
};
