unify/dev unify/dev
commit 6f8cdeaadcd7895d3a232b39a7f17922cadfdd54
Author: n.danilyuk <n.danilyuk@integrasources.com>
Date:   Mon Oct 5 17:13:25 2026 +0700

    fix(sys_bus): mirror synchronised writes after the CDC of the source bus
    
    On the 4-input board the scope cores for CH1/CH2 and CH3/CH4 run on
    adc_clk_01 and adc_clk_23. Writes to the synchronised registers (ARM,
    trigger source, trigger delay, decimation, averaging, trigger unlock) are
    mirrored from bus 1 to bus 2. Since 4da6e2f the mirror entered its own CDC,
    so ARM reached the two cores through two independent toggle synchronisers
    from FCLK and landed a cycle apart at random, while the CH1 trigger still
    crossed into the second core directly over trig_ch. Start and stop of a
    capture no longer matched between the cores and their write pointers drifted.
    The API reads all four channels at the CH1 trigger pointer, so CH3/CH4 came
    out shifted by whole samples, with stale samples at the end of the window,
    and the shift grew over time ("the signal floats").
    
    Changed:
    - sys_bus_interconnect.sv takes mirrored writes from the output of the
      SYNC_IN_BUS CDC again, as before 4da6e2f, so both cores see them on the
      same edge, the same way trig_ch reaches the second core
    - red_pitaya_4ADC.xdc bounds the crossing from the bus 1 CDC output
      registers into pll_adc_clk_1 with set_max_delay -datapath_only 8.000;
      address and data are registered one cycle before the write strobe and held
      until ACK
    - The address/data latching added to sys_bus_cdc.sv by 4da6e2f stays
    
    Only red_pitaya_top_4ADC sets SYNC_IN_BUS/SYNC_OUT_BUS*; for every other top
    the mirror logic folds away. Z20_ll and Z10 bitstreams built with this change
    are bit-identical to the current ones.
    
    Verified:
    - Z20_4 closes timing without ALLOW_TIMING_FAIL: WNS 0.035 ns, TNS 0, the
      worst path is the bounded crossing
    - STEMlab 125-14 4-Input, 1 MHz on all four inputs, 312 samples before and
      after the trigger: 0 of 300 captures shifted at decimation 1 (was 8),
      0 of 1000 with decimation cycling 1,2,1,4 (was 984), 0 of 1000 with
      1,2,1,4,1,8,1,16, 0 of 500 triggering on CH3, 0 of 5000 in a soak run;
      both cores report equal write pointers in every capture
    - 50000 random writes to trigger delay and decimation read back equal in
      both cores; split-trigger averaging matches the boxcar response on all
      four channels
    - 65-16 TI, 125-14 TI and 125-14: loopback amplitude, trigger edge position
      and inter-channel lag unchanged at decimation 1..1024
