unify/dev unify/dev
commit d2cce49eee75aa64a8b0834e324c40aeacb4fe57
Author: n.danilyuk <n.danilyuk@integrasources.com>
Date:   Thu Sep 24 13:40:16 2026 +0700

    fix(rtl_250): meter the clock arriving at the FPGA, not the halved bus clock
    
    Changed:
    - red_pitaya_hk.v takes the measured clock through new mes_clk_i / mes_rstn_i ports instead of metering clk_i
    - freq_meter result crosses from the measured clock into clk_i through two registers; both clocks come from the same MMCM at a fixed 2:1 ratio and the value changes once every 1/8 s
    - All three tops that instantiate this housekeeping drive the new ports: v0.94 and logic with adc_clk, stream_app with clk_250
    - logic and stream_app z20_250.xdc bound the meter gate crossing with set_max_delay -datapath_only 8.000, the constraint v0.94 already carried
    
    Fixed:
    - monitor -c reported 125 MHz on 250-12 because housekeeping is clocked by adc_clk2d, half the clock that reaches the FPGA; every other platform meters adc_clk, and production scripts use this value to tell whether an external clock is present
    - Without the new port connections the meter would have read 0 in logic and stream_app, and the gate crossing in those two projects missed timing by 1.3 ns once its capture side moved to 250 MHz
    
    Verified on a SIGNALlab 250-12: monitor -c reads 250002304 (was 125001152), both loopbacks and the external trigger still work; cost is 22 LUT and 58 FF.
