unify/dev unify/dev
commit 9e176e1b878a257865a8af365aa9f7c9e338d633
Author: n.danilyuk <n.danilyuk@integrasources.com>
Date:   Wed Sep 23 12:36:59 2026 +0700

    fix(rtl): align axidly_dat_o pipeline stage with its valid signal
    
    Changed:
    - axidly_dat_o now reads axi_fifo[1] instead of axi_fifo[2], matching the pipeline depth of axidly_val_o (adc_dv_r[1])
    - Applied to both rtl/classic and rtl_250/classic rp_delay.v
    
    Fixed:
    - Data output was one cycle ahead of its valid signal
