unify/dev unify/dev
commit 1014aa41b07b6a57d02e98a04b05ca8af5e492c3
Author: n.danilyuk <n.danilyuk@integrasources.com>
Date:   Thu Sep 17 16:31:39 2026 +0700

    chore(ll): fix the 65-16 chip name, tie BUFR_DIVIDE to LW, drop a dead filter
    
    Four things found while working on the LL boards. None of them changes the
    built design: both LL configurations close at the same slack as before, WNS
    0.328 ns plain and 0.484 ns with LL_ADC_65.
    
    sdc/red_pitaya_z20_ll_65.xdc called the converter an ADC3664. That is the part
    on the STEMlab 125-14 TI; the 65-16 TI carries an ADC3663. Of all the places to
    have the wrong name, the file that exists specifically to override the
    constraints for the 65-16 is the worst, since it sends the next reader to the
    wrong datasheet for the numbers it is overriding.
    
    red_pitaya_vivado_Z20_ll.tcl now records that the shipped build leaves
    LL_ADC_65 out deliberately, so one bitstream serves both boards. It is safe in
    the direction that matters: without the override the 65-16's 250 MHz ADDCLK is
    constrained as if it were 500 MHz, which demands half the period the hardware
    actually provides, and the input delays are the same numbers in either file
    because tCD is a property of the ADC output stage and does not scale with the
    bit rate. So the 65-16 just carries the extra pessimism. Nothing said this, and
    a reader had no way to tell a deliberate choice from an oversight.
    
    adc366x_top.sv computed localparam BDIV = 8/LW and then ignored it: the BUFR
    instance hardcoded "4" with the BDIV line commented out beside it. LW=2 is the
    only value built and 8/2 is 4, so the two agreed by accident. At LW=1 the
    parallel clock would have run at twice the rate the deserialiser expects, with
    nothing reporting it. BUFR_DIVIDE takes a string and cannot be written as 8/LW,
    so it now comes from a ternary on LW: "4" for the two-lane interface, "8" for
    the one-lane one, and a string BUFR rejects for anything else, which fails
    loudly instead of silently. Synthesis confirms it still binds to 4.
    
    prj/v0.94/rtl/osc_filter_ll.v is deleted. It was a copy of osc_filter.v
    differing only in the module name and trailing whitespace, referenced from
    nowhere in the repository, and since the bypass alignment work it was a stale
    copy as well, still carrying bypass_dis and the four deep delay line.
    
    Refs: A014RP-1409
